In general, integrated circuits consist of a silicon wafer on whose upper surface have been formed a number of layers, the topmost of these including several alternating layers of metal and dielectric. For low-cost packaging, it is common practice to encapsulate the structure with a layer of molded plastic. This layer of plastic is applied directly onto the topmost metal wiring, a final layer of passivation dielectric being omitted as a cost saving measure.
It has been found that there are certain problems associated with this approach. One such problem is the so-called single broken long metal line problem in which lines of wiring that are isolated on the surface (no other wiring lines close by) are subject to destruction as a result of the application of the molding plastic (usually in the form of a jet carrying significant force). Another, more general, problem is that during thermal cycling, because of thermal stress due to mismatch between the plastic and the silicon, the possibility of delamination can arise.
Referring now to FIG. 1, we show, in schematic cross-section, a portion of a silicon wafer 10 in whose upper surface various components making up integrated circuits have been formed. The inter-metal dielectric layer 11 is seen on the surface of wafer 10 with two examples of the wiring (seen in cross-section) on its top surface, shown schematically as projections 12. Covering the top surface of 11 as well as metallic wiring 12, is layer 13 of molded plastic.
In FIG. 2 we illustrate the two types of problem, discussed above, and their effect on the structures shown in FIG. 1. As a result of stress due to thermal mismatch, plastic layer 13 has delaminated, as pointed to buy Arrow 21, exposing the top surface of the structure to external contamination. Also seen is broken wire 24 which was damaged during the molding process and which (in this particular example) has been pulled away from the surface by the plastic.
One solution to the lone wire breakage problem that has been described in the prior art is the addition of extra dummy lines (unconnected to the main circuits) that help to reduce and distribute the force of the molding jet. While effective in the prevention of breakage, this solution makes a circuit susceptible to parasitic capacitor effects and is therefore undesirable from an electrical standpoint. Additionally, providing dummy lines, while reducing the probability of delamination during thermal cycling, will not always eliminate it, particularly if large uncovered areas on the surface of the final inter-metal dielectric layer still remain.
A routine search of the prior art was made but no solution to the above discussed problems similar to those of the present invention were encountered. Several references of interest were however found. For example, Bothra et al. (U.S. Pat. No. 5,618,757), as part of their process also formed dummy raised areas of oxide, but their process then goes on to fill the valleys with spin-on-glass as a way of planarizing, thereby teaching away from the present invention.
Nakano (U.S. Pat. No. 4,902,646) shows a method of forming dummy metal (as opposed to dielectric) patterns while Lee (U.S. Pat. No. 5,441,915) and Yang et al. (U.S. Pat. No. 5,798,298) both teach the dummy metal line process that we discussed above.